1. Field of the Invention
The present invention refers to a method for recognizing a defective memory cell in a memory with a plurality of memory cells and to a method for replacing recognized defective memory cells in a memory by redundant memory cells provided in the memory.
2. Description of the Related Art
Current semiconductor memory chips comprise many hundreds of millions of memory cells and can therefore no longer be produced without defects. There are always some defective memory cells in the memory. For that reason redundant memory cells are provided. In expensive test methods defective memory cells are located and finally replaced by redundant cells.
The test methods used in this context consist of reading different data structures into the memory chips and store them and then read them out again. A test device compares the read data with the originally written data. If a difference is determined, the respective cell is recognized as defective and replaced by a redundant cell. Regarding the difference, the replacement of the respective cell with a redundant cell will depend on the degree of deviation.
The problem with these test methods known in the prior art is, that the individual memory cells are only compared very abstractly against data provided by test devices by writing and reading to the memory via the test devices as described above. It is a disadvantage of this arrangement that the test conditions have to be set such that certain quality criteria are achieved in an acceptable yield. An optimum yield is just as unlikely to achieve as an optimum quality of the tested memory element.
It is the object of the present invention is to provide an improved method for recognizing a defective memory cell in a memory, as well as an improved method for replacing defective memory cells in such a memory, by which an optimum yield and an optimum quality of the memory chip are achievable.
The present invention is a method for recognizing a defective memory cell in a memory with a plurality of memory cells is provided, wherein predetermined properties of the memory cells are compared directly to one another.
According to the present invention a method for replacing defective memory cells in a memory with redundant memory cells provided in the memory is provided, wherein defective memory cells are recognized by a comparison of predetermined physical properties of the memory cells and the recognized memory cells will be replaced with redundant memory cells.
The present invention is based on the finding that instead of test methods known in prior art, where the individual memory cells are compared to test devices only very abstractly, an improved yield and quality of the corrected memory elements is achievable by comparing the memory cells directly to one another, in deviation from known test approaches. For the first time, the present invention provides the possibility of a direct comparison of memory cells to one another, wherein by a clever utilization of present circuit parts practically no additional chip space on known memory elements is necessary for the realization of the inventive method.
This is achieved by utilizing the existing structure of bit lines, word line decoders and xe2x80x9csensexe2x80x9d amplifiers for the direct comparison of memory cells. Only an addition of relatively simple logic circuit elements is necessary, that can generally be placed under already existing bus structures. Thereby, the resulting chip size is practically not influenced.
It is an advantage of the present invention that the direct comparison of predetermined properties of memory cells in a memory is made possible for the first time. It is another advantage that a practically cost free realization is made possible, since no additional chip space is necessary, due to the above-mentioned reasons.
According to a preferred embodiment of the present invention the properties of the memory cells are compared directly to one another and as a result of this comparison a monotonous series is generated, starting with the strongest memory cell and going to the weakest memory cell. According to another embodiment of the present invention it will then be possible, with the redundancy present on the memory chip, to repair defective memory cells beginning with the weakest memory cell until the whole redundancy is used up, whereby the optimum yield of memory chips with the highest quality can be achieved, since it is made sure that all redundant memory cells are used, whereas in the prior art due to the set minimum quality criteria there is a danger with the acceptable yield that redundant memory cells are not used, since certain memory cells just about achieve the minimum quality criteria. The advantage of the present invention regarding this approach is obvious, since here memory cells that would just about fulfil the minimum quality criteria are also replaced by functional redundant memory cells so that the overall quality of the memory chip is improved.